This invention relates to memory devices and particularly to flash memory devices. Flash memory devices are provided as storage in personal digital assistants, laptop and other computers, digital audio players, digital cameras, mobile phones and other electronic devices.
Flash memory is a type of EEPROM (Electrically Erasable Programmable Read-Only Memory). EEPROM flash memories are formed by arrays of semiconductor memory cells. Each of the memory cells includes a floating gate field-effect transistor having electrically isolated gates (floating gates) capable of holding a charge. The data in a cell is determined by the presence or absence of the charge on the floating gate. Charges are transported to or removed from the floating gates by specialized programming and erase operations. Flash memory is non-volatile because no power is needed to maintain the charge on the floating gates and hence no power is needed to maintain the stored information. Write fatigue of floating gate memory cells can occur after repetitive writes and erasures so that the memory cells do not properly have the correct charges.
For reading and writing of data from and to a flash memory, the cells are accessed on a random access basis to change the charge or read the charge on the floating gates. For erasing data from a flash memory, cells are grouped into sections called “erase blocks”. The charge is removed from the floating gates by block erase operations in which all floating gate memory cells in the erase block are erased in a single erase operation. In flash memory devices, a block can be written with new data only when the block is in the Erased State. Therefore, before a block can be written with new data, the block has to be erased to the Erased State. In the Erased State, all the bits in the block have the same logical state, typically a logical value of “1” so that the Erased State is an all 1's state.
A flash memory device contains multiple logically addressable pages. The logical addressable pages are usually correlated to the physical “erase block” sizes. In a typical example, an “erased block” has a size much larger than a page size. Commonly used flash devices have 4 KByte pages and 512 KByte erasable blocks. For example, pages that store between 512 bytes of data and 8 K bytes of data have between 512 8-bit cells and 8 K 8-bit cells.
In storage systems including flash memory devices, embedded operating systems (OS) manage the data stored in the flash memory devices and maintain records of which pages are in the Erased State. Only pages in the Erased State are available to store new data.
Under normal operating conditions, the operating system has full knowledge of which pages are erased pages. However, under some extraordinary conditions (for example, after power loss) the operating system's record of erased pages can be erroneous. When the erased pages record can be erroneous, the operating system goes through a detection procedure called Erased Page Detection to determine, if possible, which pages are in the Erased State.
There are difficulties presented by Erased Page Detection procedures. In flash memory systems, no indication is provided by the flash memory data as to whether or not any of the pages are in the Erased State. Erased Page Detection is done by reading the page data from a page in the flash memory. The 1's and 0's data content of the page is analyzed to determine if the content is all 1's. If all 1's, then the page may be in the Erased State. However, due to defects, frequently not all the bits are 1's when the page is in an Erased State. Also, when a page is not intended to be in an Erased State, the page nonetheless may be written with data so as to contain all 1's. Accordingly, it cannot always be determined conclusively whether a page is in the Erased State by merely analyzing the 1's and 0's data content of a page.
The ability to detect the erased or non-erased status of pages in flash memories is in part a function of the type of coding used to store data in the flash memory. In one example, BCH coding is used for flash memories.
BCH coding uses codes that are a class of parameterized, error-correcting codes which are easily decoded using syndrome decoding. Syndrome decoding is desirable since it is easily implemented with simple electronic hardware. As a class of codes, BCH codes are highly flexible and allow control over block length and acceptable error thresholds. Custom BCH codes can be easily designed according to well-known mathematical constraints. BCH codes have a code length, N, and have a correction power, T.
A page or block in flash memory is physically erased to one value, typically all 1's, and the all 1's are stored in the flash memory to represent erased values. However, it is not known whether such an all 1's sequence of values is or is not a code word. Similarly, the minimum distance from an all 1's erased sequence of values to the closest code word is not known. Under such conditions, conflicts can arise with certain types of code words to be stored as stored values in the flash memory. Codes, such as BCH codes, may have code values that conflict with the block erase states of flash memories.
Whenever the storage code values of any code words in flash memory are the same as the stored erased values in the flash memory, conflicts arise which need to be resolved. In one example, if all 0's code words are stored to flash memory with inversion to all 1's code values, then conflicts arise when the Erased State of flash memory is also all 1's values. In another example, if all 0's code words are stored to flash memory without inversion as all 0's code values, then conflicts arise when the Erased State of flash memory is also all 0's. In another example, if all 1's code words are stored to flash memory without inversion as all 1's code values, then conflicts arise when the Erased State of flash memory is also all 1's. In a still further example, if all 1's code words are stored to flash memory with inversion to all 0's code values, then conflicts arise when the Erased State of the flash memory is also all 0's. Still other conflicts between stored code values and stored erased values are possible.
It is desirable to be able to recognize in flash memory the erased or non-erased status of pages. In order to have efficient Erased Page Detection of erased pages in the flash memory that relies on the data content of the flash memory, an efficient flash memory controller is required. Efficient Erased Page Detection preferably requires no expansion or only a small expansion of the data page size and provides a large Hamming Distance between a user data page and an erased page in the flash memory.
In consideration of the above background, there is a need for improved flash memory devices that resolve conflicts between stored code words and stored erased states.